1. Technical Field
The present invention relates to a DLL (Delay Locked Loop) circuit and a method of controlling the sane. More particularly, the present invention relates to an analog DLL circuit that controls a control voltage at an initial operation so as to prevent an erroneous operation from occurring, and to a method of controlling a DLL circuit.
2. Related Art
In general, a DLL circuit is used to generate an internal clock having a phase earlier than a phase of a reference clock that is obtained through conversion of an external clock. In a semiconductor integrated circuit having relatively high integration, such as a synchronous DRAM (SDRAM) or the like, the internal clock that is synchronous with data needs to be in phase with the external clock.
Specifically, the external clock is input to a clock input buffer through an input pin of the semiconductor integrated circuit. The clock input buffer outputs the internal clock. Thereafter, the internal clock controls a data output buffer for data output. At this time, due to the clock input buffer, the internal clock has a phase delayed more than a phase of the external clock. Further, the internal clock is further delayed by delay elements in the semiconductor integrated circuit and then transmitted to the data output buffer.
Accordingly, the output data may be output after a large amount of time has elapsed as compared with the external clock, that is, a data output time after the external clock is applied, which means an output data access time may be extended.
The DLL circuit is used in order to solve this problem. The DLL circuit sets the phase of the internal clock to be earlier by a predetermined time than the external clock. Accordingly, the output data is output without delay with respect to the external clock. That is, the DLL circuit receives the external clock and generates the internal clock having a phase earlier than the external clock.
The DLL circuit includes a clock input buffer that converts the amplitude of the external clock so as to generate the reference clock. The reference clock is used for comparison with the phase of a feedback clock in a phase comparator. Further, the reference clock is used as an input signal of a delay line that generates the internal clock under the control of a shift register.
An analog DLL circuit divides the phase of the reference clock so as to generate a plurality of divided clocks, selects one clock among the plurality of divided clocks according to the phase comparison result of the reference clock and the feedback clock, and inputs the selected clock to the delay line. Further, the analog DLL circuit compares the phase of the reference clock with the phase of the feedback clock, generates the control voltage according to the comparison result, and supplies the control voltage to the delay line. Then, the phase of a delay clock to be generated by the delay line is controlled according to the level of the control voltage. For example, if the level of the control voltage exceeds a reference level, the delay line performs an operation to delay the phase of the input clock. Meanwhile, if the level of the control voltage is less than the reference level, the delay line performs an operation to advance the phase of the input clock.
Hereinafter, the DLL circuit according to the related art will be described with reference to the accompanying drawings.
FIGS. 1A and 1B are timing diagrams illustrating the operation of the DLL circuit according to the related art.
In FIGS. 1A and 1B, the reference clock clk_ref and the feedback clock clk_fb in the related art are shown.
As shown in FIG. 1A, when the phase of the feedback clock clk_fb precedes the phase of the reference clock clk_ref, the phase of the feedback clock clk_fb needs to be delayed and then synchronized with the phase of the reference clock clk_ref. In this case, the delay amount of a delay line needs to be increased. Accordingly, an operation to increase the level of the control voltage needs to be performed.
As shown in FIG. 1B, when the phase of the reference clock clk_ref precedes the phase of the feedback clock clk_fb, the phase of the feedback clock clk_fb needs to be advanced and then synchronized with the phase of the reference clock clk_ref. In this case, the delay amount of the delay line needs to be reduced. Accordingly, an operation to lower the level of the control voltage needs to be performed.
During the initial operation of the DLL circuit according to the related art, the phase of the reference clock clk_ref and the phase of the feedback clock clk_fb may be the same as each other. In this case, the control voltage to be generated by the delay control unit has a level of the ground voltage. At this time, if a DLL power supply voltage falls, the feedback clock clk_fb is delayed to establish the phase relationship shown in FIG. 1B. As shown in FIG. 1B, when the phase of the feedback clock clk_fb needs to be advanced, the level of the control voltage needs to be lowered. However, since the potential of the control voltage is the same as that of the ground voltage, the corresponding operation is not performed. In this case, the DLL circuit does not operate normally. As such, during the initial operation of the DLL circuit according to the related art, an erroneous operation may occur due to the level of the control voltage and the phase of the clock.